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This role involves hands-on experience with DFT aspects such as scan insertion, memory built-in self-test (MBIST), and JTAG, as well as ATPG and pattern validation both at the block and full chip level. Working with tools from Synopsys, Cadence, and Mentor Graphics is essential.
Position:
Engineer (DFT)
Job Description:
:- Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level
- Synopsys tools: DFT MAX, TetraMAX
OR
- Cadence tools: RTL Compiler, Encounter Test , modus, Janus
OR
- Mentor Graphics tools: Tessent tool chain, TestKompress
- Debussy, VCS/Questa/IUS
- PT tool from Synopsys
Location:
IN-KA-Bangalore, India (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services
Top Skills
Dft
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