The Design Engineer II will handle block level netlist to GDS delivery, manage subsystem PnR, and achieve timing closure, requiring 3+ years of relevant experience.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. Invecas is a wholly owned subsidiary of Cadence.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
Qualifications
- BE/BTech/ME/MS/MTech in Electrical/Electronics or Equivalent
Role : Design Engineer 2, Digital Physical Desing
- Responsibilities
- Block level Netlist to GDS delivery
- Subsystem level PnR and timing closure
- Required Skills
- 3+ years of experience in PnR and STA
- Handson experience in RTL/Netlist to GDS delivery of blocks
- Good exposure to Placement, CTS and Routing techniques
- Capable of doing PV and IREM fixes along with timing
- Good exposure to Cadence EDA tool set needed for PD
- TCL and PERL scripting knowledge and experience in writing the scripts
- Optional Skills
- Complex blocks floorplan, PnR and STA
- Complex IP integration like DDR and PCIe
- Hands on experience in low power designs
- Good understanding of DFT stitching
- Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
Qualifications
- BE/BTech/ME/MS/MTech in Electrical/Electronics
Top Skills
Cadence Eda Tool Set
Gds
Netlist
Perl
Pnr
Rtl
Sta
Tcl
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